In your new job you will: Create new and improve existing verification environments Apply Universal Verification Methodology (UVM) Define verification plans and setup verification metrics in digital and mixed-signal environments Execute tests in these environments on RTL and gate-level Closely cooperate with analog and digital designers as well as concept and verification engineers
You work conscientiously on making things better, faster, and more efficient and keep up high quality standards for yourself and other people. Your ability to quickly establish a successful cooperation helps you to gain trust within the team. Furthermore, you demonstrate strong communication skills and know how to establish lasting relationships and networks. Your profile
You are best equipped for this task if you have: A degree in Electrical Engineering, Information Technology or Telematics with focus on electronics First related work ex perience Good knowledge of VHDL, Verilog, C Good knowledge of Unix programming languages such as Shell, Perl, TCL etc Experience at any level in Specman/e, SystemVerilog Knowledge of SVAs, PSL, formal or mixed-signal verification as a plus Functional verification experience as a plus Fluent English skills or German skills as a plus
We are filling this position through one of our leasing partners. A valid work permit for Austria or EU citizenship is a prerequisite for this position. This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group G (https://www.feei.at/leistungen/informations-service/mindestlohne-und-gehalter-2020). The monthly salary is paid 14 times p.a. A higher payment is negotiable depending on your expertise and skills.
- Arbeitsstunden pro Woche
- 4 - 40
- Veröffentlicht am
- Verkauf / Retail
- Führerschein erforderlich?
- Auto erforderlich?
- Motivationsschreiben erforderlich?